? semiconductor components industries, llc, 2006 july, 2006 ? rev. 8 1 publication order number: p6smb11cat3/d p6smb11cat3 series 600 watt peak power zener transient voltage suppressors bidirectional* the smb series is designed to protect voltage sensitive components from high voltage, high energy transients. they have excellent clamping capability, high surge capability, low zener impedance and fast response time. the smb series is supplied in on semiconductor?s exclusive, cost-effective, highly reliable surmetic package and is ideally suited for use in communication systems, automotive, numerical controls, process controls, medical equipment, business machines, power supplies and many other industrial/consumer applications. features ? working peak reverse voltage range ? 9.4 to 77.8 v ? standard zener breakdown voltage range ? 11 to 91 v ? peak power ? 600 w @ 1 ms ? esd rating of class 3 (>16 kv) per human body model ? maximum clamp voltage @ peak pulse current ? low leakage < 5 a above 10 v ? ul 497b for isolated loop circuit protection ? response time is typically < 1 ns ? pb?free packages are available mechanical characteristics: case: void-free, transfer-molded, thermosetting plastic finish: all external surfaces are corrosion resistant and leads are readily solderable maximum case temperature for soldering purposes: 260 c for 10 seconds leads: modified l?bend providing more contact area to bond pads polarity: polarity band will not be indicated mounting position: any maximum ratings rating symbol value unit peak power dissipation (note 1) @ t l = 25 c, pulse width = 1 ms p pk 600 w dc power dissipation @ t l = 75 c measured zero lead length (note 2) derate above 75 c thermal resistance, junction?to?lead p d r jl 3.0 40 25 w mw/ c c/w dc power dissipation (note 3) @ t a = 25 c derate above 25 c thermal resistance, junction?to?ambient p d r ja 0.55 4.4 226 w mw/ c c/w operating and storage temperature range t j , t stg ?65 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. 10 x 1000 s, non?repetitive 2. 1 square copper pad, fr?4 board 3. fr?4 board, using on semiconductor minimum recommended footprint, as shown in 403a case outline dimensions spec. *please see p6smb6.8at3 to p6smb200at3 for unidirectional devices. plastic surface mount zener overvoltage transient suppressors 9.4?78 volts 600 watt peak power devices listed in bold, italic are on semiconductor preferred devices. preferred devices are recommended choices for future use and best overall value. device package shipping ? ordering information p6smbxxcat3 smb 2500/tape & reel smb case 403a plastic marking diagram http://onsemi.com ayww xxc xxc = device code a = assembly location y = year ww = work week = pb?free package (note: microdot may be in either location) p6smbxxcat3g smb (pb?free) 2500/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. the ?t3? suffix refers to a 13 inch reel.
bi?directional tvs i pp i pp v i i r i t i t i r v rwm v c v br v rwm v c v br p6smb11cat3 series http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) symbol parameter i pp maximum reverse peak pulse current v c clamping voltage @ i pp v rwm working peak reverse voltage i r maximum reverse leakage current @ v rwm v br breakdown voltage @ i t i t test current v br maximum temperature coefficient of v br electrical characteristics (devices listed in bold, italic are on semiconductor preferred devices.) device* device marking v rwm (note 4 ) i r @ v rwm breakdown voltage v c @ i pp (note 6) v br c typ (note 7) v br volts (note 5) @ i t v c i pp volts a min nom max ma volts amps %/ c pf p6smb11cat3, g p6smb12cat3, g p6smb13cat3, g 11c 12c 13c 9.4 10.2 11.1 5 5 5 10.5 11.4 12.4 11.05 12 13.05 11.6 12.6 13.7 1 1 1 15.6 16.7 18.2 38 36 33 0.075 0.078 0.081 865 800 740 p6smb15cat3, g p6smb16cat3, g p6smb18cat3, g p6smb20cat3, g 15c 16c 18c 20c 12.8 13.6 15.3 17.1 5 5 5 5 14.3 15.2 17.1 19 15.05 16 18 20 15.8 16.8 18.9 21 1 1 1 1 21.2 22.5 25.2 27.7 28 27 24 22 0.084 0.086 0.088 0.09 645 610 545 490 p6smb22cat3, g p6smb24cat3, g p6smb27cat3, g p6smb30cat3, g 22c 24c 27c 30c 18.8 20.5 23.1 25.6 5 5 5 5 20.9 22.8 25.7 28.5 22 24 27.05 30 23.1 25.2 28.4 31.5 1 1 1 1 30.6 33.2 37.5 41.4 20 18 16 14.4 0.09 0.094 0.096 0.097 450 415 370 335 p6smb33cat3, g p6smb36cat3, g p6smb39cat3, g p6smb43cat3, g 33c 36c 39c 43c 28.2 30.8 33.3 36.8 5 5 5 5 31.4 34.2 37.1 40.9 33.05 36 39.05 43.05 34.7 37.8 41 45.2 1 1 1 1 45.7 49.9 53.9 59.3 13.2 12 11.2 10.1 0.098 0.099 0.1 0.101 305 280 260 240 p6smb47cat3, g p6smb51cat3, g p6smb56cat3, g p6smb62cat3, g 47c 51c 56c 62c 40.2 43.6 47.8 53 5 5 5 5 44.7 48.5 53.2 58.9 47.05 51.05 56 62 49.4 53.6 58.8 65.1 1 1 1 1 64.8 70.1 77 85 9.3 8.6 7.8 7.1 0.101 0.102 0.103 0.104 220 205 185 170 p6smb68cat3, g p6smb75cat3, g p6smb82cat3, g p6smb91cat3, g 68c 75c 82c 91c 58.1 64.1 70.1 77.8 5 5 5 5 64.6 71.3 77.9 86.5 68 75.05 82 91 71.4 78.8 86.1 95.5 1 1 1 1 92 103 113 125 6.5 5.8 5.3 4.8 0.104 0.105 0.105 0.106 155 140 130 120 4. a transient suppressor is normally selected according to the working peak reverse voltage (v rwm ), which should be equal to or greater than the dc or continuous peak operating voltage level. 5. v br measured at pulse test current i t at an ambient temperature of 25 c. 6. surge current waveform per figure 2 and derate per figure 3 of the general data ? 600 watt at the beginning of this group. 7. bias voltage = 0 v, f = 1 mhz, t j = 25 c *the ?g?? suffix indicates pb?free package available. please refer back to ordering information on front page.
p6smb11cat3 series http://onsemi.com 3 p , peak power (kw) p nonrepetitive pulse waveform shown in figure 2 t p , pulse width 1 10 100 0.1 s1 s10 s 100 s 1 ms 10 ms 0.1 figure 1. pulse rating curve 01234 0 50 100 t, time (ms) value (%) half value ? i pp 2 peak value ? i pp t r 10 s figure 2. pulse waveform typical protection circuit v in v l z in load figure 3. pulse derating curve peak pulse derating in % of peak power or current @ t a = 25 c 100 80 60 40 20 0 0 25 50 75 100 125 150 t a , ambient temperature ( c) 120 140 160 t p pulse width (t p ) is defined as that point where the peak current decays to 50% of i pp . figure 4. typical junction capacitance vs. bias voltage p6smb11cat3g p6smb18cat3g P6SMB47CAT3G p6smb91cat3g bias voltage (volts) 11010 0 10 100 1000 c, capacitance (pf) 1 5 t j = 25 c f = 1 mhz
p6smb11cat3 series http://onsemi.com 4 application notes response time in most applications, the transient suppressor device is placed in parallel with the equipment or component to be protected. in this situation, ther e is a time delay associated with the capacitance of the device and an overshoot condition associated with the inductance of the device and the inductance of the connection method. the capacitive effect is of minor importance in the parallel protection scheme because it only produces a time delay in the transition from the operating voltage to the clamp voltage as shown in figure 4. the inductive effects in the device are due to actual turn-on time (time required for the device to go from zero current to full current) and lead inductance. this inductive effect produces an overshoot in the voltage across the equipment or component being protected as shown in figure 5. minimizing this overshoot is very important in the application, since the main purpose for adding a transient suppressor is to clamp voltage spikes. the smb series have a very good response time, typically < 1 ns and negligible inductance. however, external inductive effects could produce unacceptable overshoot. proper circuit layout, minimum lead lengths and placing the suppressor device as close as possible to the equipment or components to be protected will minimize this overshoot. some input impedance represented by z in is essential to prevent overstress of the protection device. this impedance should be as high as possible, without restricting the circuit operation. duty cycle derating the data of figure 1 applies for non-repetitive conditions and at a lead temperature of 25 c. if the duty cycle increases, the peak power must be reduced as indicated by the curves of figure 6. average power must be derated as the lead or ambient temperature rises above 25 c. the average power derating curve normally given on data sheets may be normalized and used for this purpose. at first glance the derating curves of figure 6 appear to be in error as the 10 ms pulse has a higher derating factor than the 10 s pulse. however, when the derating factor for a given pulse of figure 6 is multiplied by the peak power value of figure 1 for the same pulse, the results follow the expected trend.
p6smb11cat3 series http://onsemi.com 5 v l v v in v in (transient) v l t d v v in (transient) overshoot due to inductive effects t d = time delay due to capacitive effect t t figure 5. figure 6. figure 7. typical derating factor for duty cycle derating factor 1 ms 10 s 1 0.7 0.5 0.3 0.05 0.1 0.2 0.01 0.02 0.03 0.07 100 s 0.1 0.2 0.5 2 5 10 50 1 20 100 d, duty cycle (%) pulse width 10 ms ul recognition the entire series has underwriters laboratory recognition for the classification of protectors (qvgv2) under the ul standard for safety 497b and file #116110. many competitors only have one or two devices recognized or have recognition in a non-protective category. some competitors have no recognition at all. with the ul497b recognition, our parts successfully passed several tests including strike voltage breakdown test, endurance conditioning, temperature test, dielectric voltage-withstand test, discharge test and several more. whereas, some competitors have only passed a flammability test for the package material, we have been recognized for much more to be included in their protector category.
p6smb11cat3 series http://onsemi.com 6 package dimensions smb do?214aa case 403a?03 issue f e b d c l1 l a a1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. d dimension shall be measured within dimension p. 2.261 0.089 2.743 0.108 2.159 0.085 mm inches scale 8:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dim a min nom max min millimeters 1.90 2.13 2.45 0.075 inches a1 0.05 0.10 0.20 0.002 b 1.96 2.03 2.20 0.077 c 0.15 0.23 0.31 0.006 d 3.30 3.56 3.95 0.130 e 4.06 4.32 4.60 0.160 l 0.76 1.02 1.60 0.030 0.084 0.096 0.004 0.008 0.080 0.087 0.009 0.012 0.140 0.156 0.170 0.181 0.040 0.063 nom max 5.21 5.44 5.60 0.205 0.214 0.220 h e 0.51 ref 0.020 ref d l1 h e on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 p6smb11cat3/d surmetic is a trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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